SYMPOSIUM C

11:00 AM *C1-S2.1 (invited)
Spin and Valley Degree of Freedom in Silicon Quantum Structures. (#1398) Yoshiro Hirayama, Tohoku University & ERATO Nuclear Spin Electronics Project, Sendai, Miyagi, Japan.

Silicon quantum wells possess unique electronic band structure arising from both spin and valley degrees of freedom. We have demonstrated that the electronic subband structrures can be evaluated from step or kink in the conductance, reflecting enhanced scattering by the occupation of a new subband [1]. By using this technique, a large valley spliting is clearly revealed in SIMOX Si quantum wells at zero magnetic field when electrons are pushed to the ion-implanted burried oxide interface. The data clearly indicate a valley splitting tunable by the front and back gate biases [1,2]. The similar technique can be applied to resolve the spin splitting of the upper subband edge under in-plane magnetic field [3]. The controlled spin and valley splitting enables us to access anomalous quantum Hall effect originating from the combined degeneracy due to the spin and valley degrees of freedom [4]. A novel magnetic field and temperature dependence of the resistance observed around the occupation of the upper subband is also investigated by controlling the spin and valley degrees of freedoms [5]. In addition to Si quantum wells, a gate-defined Si quantum dot is expected as a promising device for the future nanoelectronics and quantum information processings. Recently, the fully tunable Si double quantum dot has been demonstrated by optimizing structural parameters [6,7]. The valley degeneracy is lifted in such quantum dot systems. Moreover, we have successfully demonstrated a spin-blockade feature in unintentionally-formed small-size coupled quantum dot [8], suggesting a possibility of the spin manipulation and detection in the Si quantum dot systems. These studies were carried out mainly in NTT Basic Research Labs. in collaboration with K. Takashina, A. Fujiwara, T. Fujisawa (NTT), Y. Niida (Tohoku Univ.), and H. Liu (ERATO & Jilin Univ.).

[1] K. Takashina et al., Phys. Rev. Lett. 96, 236801 (2006). [2] K. Takashina , et al., Phys. Rev. B69, 161304(R) (2004). [3] Y. Niida et al., presented at SSDM2007 (to be published). [4] K. Takashina et al., Phys. Rev. Lett. 99, 036803 (2007). [5] K. Takashina et al., submitted to HMF2008. [6] A. Fujiwara et al., Appl. Phys. Lett. 88, 053121 (2006). [7] H. W. Liu et al., to be published. [8] H. W. Liu et al., Phys. Rev. B77, 073310 (2008).

11:30 AM *C1-S2.2 (invited)
Quantum Dots and Radio-Frequency Single Electron Transistors in Silicon. (#366) Susan Jane Angus¹, Andrew Ferguson², Andrew Dzurak³, Robert Clark³; ¹The University of Melbourne, Parkville, Victoria, Australia ; ²University of Cambridge, United Kingdom ; ³The University of New South Wales, Sydney, Australia.

We report the fabrication and measurement of silicon quantum dots which are created using tunable tunnel barriers in a narrow channel field effect transistor. A native aluminium oxide layer is used to electrically isolate two layers of aluminium gates. This double layer of gates allows independent control over the electron density in the dot and the coupling of the dot to the leads. This AlOx technique has not previously been used in silicon devices and enables the creation of small (&sim 50nm diameter) dots. Low-temperature transport spectroscopy has been performed, in both the many electron (&sim 100 electrons) and the few electron (&sim 10 electrons) regimes. Periodic Coulomb diamonds have been observed over a large range of applied gate bias, confirming the electrostatic definition of a single dot. Excited states observed in the bias spectroscopy in the few electron regime provide evidence of quantum confinement. These results demonstrate that depletion gates are an effective technique for defining quantum dots in silicon. In addition, we present the operation of this device as a silicon radio frequency single electron transistor (rf-SET). The island is again defined by electrostatically tunable tunnel barriers in a narrow channel field effect transistor. Charge sensitivities of better than 10 µ e &frasl &radic Hz have been demonstrated at MHz bandwidth, indicating that silicon may be used to fabricate fast, sensitive electrometers. Furthermore, the silicon rf-SET has now been demonstrated at 4.2K, opening up the possibility of radio frequency charge detection without the need for millikelvin temperatures.

12:00 PM C1-S2.3
Ion Implantation through Thin Silicon Dioxide Layers for Si-Based Solid-State Quantum Computer Device Development. (#854) Jeffrey Colin McCallum¹, Michael Dunn¹, Eric Gauja²; ¹The University of Melbourne, Parkville, Victoria, Australia ; ²The University of New South Wales, Sydney, Australia.

Ion implantation doping of Si through an SiO2 overlayer is of interest for fabrication of advanced MOSFET's and for a range of devices of interest in the development of a solid-state quantum computer (SSQC). SSQC-related devices that are currently being fabricated include structures in which spin-dependent transport is measured, or where charge transfer occurs between quantum dots or between individual donors. The implantation requirements of these devices cover ion fluences in the 1011 - 1014 cm-2 regime at energies typically in the range 10 - 20 keV and usually require implantation through a pre-existing thin device-quality thermal oxide. The subsequent thermal processing steps that are required to activate the implanted ions and repair the oxide and substrate damage should also ideally result in very limited diffusion of the implanted ions. Deep level transient spectroscopy (DLTS) in its various forms provides a convenient means of identifying and quantifying the electrically-active defects introduced within the bulk and at the SiO2-Si interface by the oxide-growth and implantation processes and it can be used to monitor their removal via subsequent annealing steps. Of particular importance to the solid-state quantum computer fabrication program is the fact that DLTS measurements on metal-oxide semiconductor (MOS) structures allow the near-oxide interface region to be probed at sensitivities that are suitable for the ion fluence regime of interest and more importantly at defect densities that could adversely affect quantum device operation. In this presentation we will describe some of the key device structures that are currently being explored in the process of developing Si-based solid state quantum computing devices and present results from our DLTS studies of as-grown and ion-implanted structures. We will describe post oxide growth processing that can be used to reduce interface trap densities to levels suitable for development of quantum devices and present data for ion implanted (P, Si or N) and rapid-thermally processed devices. For thin oxides of 5nm or less and low ion fluences we find that implantation does not significantly increase interface trap densities and somewhat surprisingly that it can even be beneficial when the interface trap density is abnormally high (~ 1e11 cm-2.eV-1) for the as-grown oxide. The implications of these studies for solid-state quantum computer development will be discussed.

12:15 PM C1-S2.4
Developments in the Enhancement of Band-Edge Luminescence in Silicon for Future Light Emitting Devices. (#962) Byron John Villis, Paul G Spizzirri, Brett C Johnson, Jeffrey C McCallum; The University of Melbourne, Parkville, Victoria, Australia.

As the number of transistors on a single silicon computer device increases, the time taken for an electrical pulse to travel from one component to the next has gradually become significant in the overall processing time taken to perform a calculation. The recognised solution to this interconnect problem is to use light to transmit these signals. The optimum material to use would be Si so as to avoid the addition of another semiconductor material, further complicating the already challenging fabrication process. An obvious problem with using Si for light emission is that it has an indirect band-gap and hence it has a poor light emission efficiency. In recent years there has been an increase in the number of papers discussing methods to enhance the weak band-edge luminescence observed at approximately 1.1 um. Much of this literature discusses the process of boron implantation followed by a high temperature anneal to create an extended defect network. It has been observed from devices fabricated using this technique that both the Electroluminescence (EL) and Photoluminescence (PL) band-edge peak intensity increases significantly. Although the enhancement mechanism is still a matter of some controversy, two possible mechanisms have been proposed. In the first model, extended defects form dislocation loops which create a strain layer capable of confining excitons. These excitons are then prevented from recombining through non-radiative pathways and must hence eventually recombine radiatively through the absorption of a phonon and the emission of a photon. In the second model, the implanted B creates excess charge carriers and the dislocation loops only aid in the process of gettering the impurities that would normally assist the non-radiative recombination of the excitons. In the work presented here we have tried to shed some light on this controversial topic through the use of PL using two different excitation lasers. The different wavelengths of these lasers allow for the excitation of charge carriers in different regions in the Si substrate, either in close proximity to the dislocation band or deep within the bulk. For this work we have compared the band-edge luminescence from ultra pure, lightly dope, float zone Si with Czochralski-grown Si wafers with a higher initial doping profile. These measurements were preformed through a range of cryogenic temperatures up to room temperature. With these wafers we have performed similar processing steps as described by the literature to create extended defects through the process of B implantation. Here we have also extended our investigation to look at the luminescence from defect free regions which have also undergone the implantation of B, achieved through laser annealing. We have also investigated the effect of surface treatment on this band-edge luminescence through either the careful growth of a low defect surface oxide formed in a triple walled furnace or via the hydrogen-termination of the surfaces.

LUNCH 12:30 PM - 2:00 PM

2:00 PM *C1-S3.1 (invited)
Addressing the Charge and Spin of a Single Dopant Atom in a Nano MOSFET. (#1394) Sven Rogge, Kavli Institute of NanoScience, Delft University of Technology, Netherlands.

Current semiconductor devices have been scaled to such dimensions that we need take atomistic approach to understand their operation for nano-electronics. From a bottoms-up perspective, the smallest functional element within a nano-device would be a single (dopant) atom itself. Control and understanding over the properties of a single dopant could proof a key ingredient for device technology beyond-CMOS. Here, we will discuss resonant tunneling spectroscopy measurements of single As donors in a three terminal configuration, i.e. a gated donor. The donors are incorporated in the channel of (p-type) prototype transistors called FinFETs. These devices provide us with electrical access to a single donor and we can control the charge of the donor by means of the gate. The local electric field due to the built-in voltage between the channel and the gate electrode forms a triangular potential at the interface. We will show that by means of spectroscopic measurements we can identify the excited states and associate them with either the donors Coulomb potential, the triangular well or a hybridized combinations of the two. The theoretical framework used to describe this system (NEMO 3-D) is based on a multimillion atom tight binding simulation. The correspondence between the transport measurements, the theoretical model and the local environment of the donor provides a robust atomic understanding of actual gated donors in a nanostructure. We furthermore observe a Kondo resonance in the transport through the donor when it is charged with a single electron. The identification is made by the magnetic field splitting and the temperature dependence of the resonance. We have experimental evidence that the Kondo resonance is of SU(4) nature, i.e. an entanglement between the spin and orbital degree of freedom of the donor. The orbital degree of freedom is formed by the overlap (in energy) of the ground- and first excited -state of the donor. The presence of Kondo effect in our devices give us access to the spin degree of freedom of the donor.

2:30 PM *C1-S3.2 (invited)
STM-Patterned P-donor Based Planar Quantum Dot Structures in Silicon. (#1013) Martin Fuechsle, Andreas Fuhrer, Thilo C. G. Reusch, Michelle Y. Simmons; Centre for Quantum Computer Technology, School of Physics, The University of New South Wales, Sydney, Australia.

We demonstrate a fully UHV-based fabrication scheme for STM-patterned planar, highly phosphorus doped quantum dot structures on a Si(100) surface. This technique allows for atomically precise, multi-terminal, in-plane gated donor-based quantum devices. We present electrical transport measurements on an optimized five-terminal 40 x 50 nm^2 quantum dot containing roughly 4000 electrons. Using an in-plane plunger gate, we observe remarkably stable Coulomb oscillations up to 4K. By adding an EBL-defined metallic top-gate, patterned on the native oxide barrier, we are able to tune the electron number on the dot by ~360. At temperatures below 1K, we observe clear Coulomb oscillations as a function of top-gate voltage. Also, by applying a top-gate voltage, we are able to tune the gate-range of the in-plane barrier gates from 0 to more than 1V. Our current investigations focus on the electronic properties of the tunnelling barriers as well as the impact of a metallic top-gate on device stability. Future devices will focus on going towards the few electron regime by reducing the size of the island. The intricate change of cross-capacitances within the dot structure associated with downscaling necessitates careful considerations in terms of device geometry in order to achieve full depletion.

3:00 PM C1-S3.3
Towards 3D Silicon Device Fabrication: The Effect of Incorporation Temperature on Activation and Encapsulation of P:Si Delta-Doped Layers. (#990) Sarah Rose McKibbin, The University of New South Wales, Sydney, Australia.

S. R. McKibbin1, A. Fuhrer1, T.C.G. Ruesch2, W.R. Clarke1, M. Y. Simmons1,2. 1School of Physics, University of New South Wales, Sydney, New South Wales 2052, Australia 2Centre for Quantum Computer Technology, School of Physics, University of New South Wales, Sydney, New South Wales 2052, Australia We have recently demonstrated that STM lithography can be used to define novel- nano Si:P devices using a hydrogen resist on a Si(001) surface {F.J. Reuss, Nanoletters, (2004)}. The electrical properties of these buried, planar devices is strongly affected by the temperature used to incorporate the P dopants into the silicon lattice and dissociate the original PH3 dopant source. A 550?C anneal used to fully incorporate P into Si lattice sites and remove the dissociated hydrogen is not suitable for maintaining the nanoscale device pattern since the high temperature anneal removes the hydrogen resist. However if hydrogen is not completely removed before the silicon growth the quality of the low temperature Si growth employed to encapsulate the completed device is reduced. With growing interest into 3D device fabrication for integrated circuits, there has been ignited interest in improving the encapsulation of devices so that we may pattern multiple layers stacked on one another vertically. To this end we have fabricated P:Si delta-doped layers with different incorporation temperatures to observe the effect of the presence of hydrogen on the silicon encapsulation quality and the effect this has on electrical device properties. We present STM images of the delta-doped layer after incorporation and encapsulation showing how epitaxial quality increases with higher incorporation anneals and how the overall resultant surface morphology depends on how well the PH3 is dissociated. We present electrical magnetoresistance traces at 4K which show that dopant activation and mobilities decrease with increasing anneal temperature. A maximum 2D carrier density of 2.4x1014cm-2 was obtained by a 350?C incorporation anneal. Here we have a surface coverage of 0.33 monolayers which achieve full activation - higher than the previously predicted maximum of 0.25 monolayers of P on Si(001) {D. S. Lin, Surface Sci 424 (1999) }.

3:15 PM C1-S3.4
Fabrication and Characterizations of Atomically-Controlled Fe₃Si/Ge Heterostructures for Spin-Transistors with Ge Channel. (#285) Masanobu Miyao¹, Koji Ueda¹, Yuichiro Ando¹, Mamoru Kumano¹, Yuji Kishi¹, Taizoh Sadoh¹, Kazumasa Narumi², Yusuke Hiraiwa³, Yoshihito Maeda³, Yukio Nozaki¹, Kimihide Matsuyama¹; ¹Department of Electronics, Kyushu University, Fukuoka, Japan ; ²Japan Atomic Energy Agency, Japan ; ³Kyoto University, Japan.

   Ferromagnetic silicide Fe₃Si (Curie temperature: 567^oC) has three phases (A2, B2, and DO₃), where the DO₃-type is an ordered phase and calculated to be spin-polarized at the Fermi level. In addition, the lattice constant (0.565 nm) of Fe₃Si is almost completely equal to that of Ge. Therefore, atomically controlled epitaxial growth of Fe₃Si is expected on Ge, which enables injection of spin-polarized electrons through the Fe₃Si/Ge interface. This will be a powerful tool to realize Ge channel spin transistors with ultra-high speed-operation and ultra-low power-consumption. This paper reports our recent progress in novel epitaxial growth of Fe₃Si on Ge for the application of group IV-based spin-transistors.    In the experiment, Fe and Si were co-evaporated (60-200^oC) on Ge substrates with (100), (110), and (111) orientations by using MBE system. In-situ RHEED experiments indicated that sub-layer coverage by Fe/Si atoms formed amorphous layers covering substrates. The grown layers suddenly changed into a crystalline phase when Fe/Si atoms to form 1ML Fe₃Si were arrived. From RBS axial-channeling measurements, large values of the minimum yield (χ_min) exceeding 65% were obtained for (100) and (110) substrates. These values were drastically decreased to less than 7% by substituting (111) substrates.    Detailed experiments indicated that both Fe/Si ratio and growth temperature were key factors to improve interface quality of Fe₃Si/Ge (111). Very low χ_min of 2.2% was achieved by tuning Fe/Si ratio exactly to 3/1 and optimizing growth temperature (130^oC). Cross-sectional TEM observation demonstrated the atomically flat interface of Fe₃Si/Ge (111). In addition, its electron diffraction pattern indicated strong super-lattice reflection spots, which confirmed the formation of ordered DO₃-type Fe₃Si layers.    Magnetic properties were evaluated by using the vibrating sample magnetometry, which showed the growth-temperature dependent coercivities. A smallest value (0.8 Oe) was obtained from the sample with highest crystal quality (χ_min : 2.2 %). Weak uniaxial anisotropy supposed to originate from a uniaxial lattice strain was observed, where the anisotropy field was very small (7 Oe). Consequently, formation of source/drain electrodes with uniform magnetic properties is expected to be realized by using the shape anisotropy.    Electrical properties were also evaluated by using current-voltage and capacitance-voltage measurements, which indicated good Schottky characteristics with the barrier height of 0.5 eV. The ratio of the on-current to the off-current was the order of 10⁴. Annealing experiments after growth (i.e. post-annealing) were also performed. Results guaranteed the thermal stability of such good electrical properties up to 400^oC.    These results will be a powerful tool to realize new-type group IV-based spin-transistors, i.e., Ge channel with high mobility and Fe₃Si source/drain for spin-injection.

AFTERNOON BREAK 3:30 PM - 4:00 PM

4:00 PM *C1-S4.1 (invited)
Ge-On-Insulator Substrates Formed by Ge Condensation Technique: Fabrication, Modeling and Characterization. (#1395) Jean-François Damlencourt¹, B. Vincent¹, C. Le Royer¹, P. Rivallin¹, E. Martinez¹, M.C. Roure¹, Y. Campidelli², D. Rouchon¹, T. Nguyen³, S. Cristoloveanu³, Y. Morand², S. Descombes², L. Clavelier¹; ¹CEA-DRT-LETI - CEA/GRE, Grenoble, France ; ²ST Microelectronics, Grenoble, France ; ³IMEP-INP Grenoble-Minatec, France.

Germanium is today considered as one of the most adapted semiconductor substitutes of Silicon for ultimate device scaling having an identical crystalline structure and higher carrier mobility. For MOS Field Effect Transistor (MOSFET) fabrication, Germanium needs nevertheless to be used On Insulator; the junction capacitance and leakage currents are then reduced while the "On Insulator" electrostatic advantages greatly improve the short-channel effects. The Ge condensation technique is a promising avenue for GeOI substrates fabrication.^{1, 2} In this paper, we will present the synthesis of high quality GeOI substrates (full sheet and local) by condensation technique. A tool, to predict the Ge enrichment kinetic, has been developed by TCAD simulation and analytical calculations. This tool allows investigating the impact of process parameters on the film thickness and composition uniformities. The main results will be presented. Finally, we will highlight the electrical quality of the GeOI substrates, assed by the pseudoMOS technique,³ as well as the performance of deep sub-micron pMOSFETs elaborated on ultra thin GeOI wafers. 1 T.Tezuka et al., Appl. Phys. Lett., 79, 1798 (2001). 2 T.Tezuka et al., Jpn. J. Appl. Phys, 40, 2866 (2001). 3 Cristoloveanu et al., IEEE TED, vol 47, No. 5, 2000.

4:30 PM C1-S4.2
A Nanoscopic Investigation on Thermal Decomposition of Ultrathin Silicon Oxide by High Temperature Scanning Tunneling Microscopy. (#520) Jian-Bin Xu, Kun Xue, Aaron H.P. Ho; Department of Electronic Engineering, The Chinese University of Hong Kong, Hong Kong.

A quasi two-dimensional surface chemical reaction - the thermal decomposition of ultrathin silicon oxide (~1nm) by ultrahigh vacuum (UHV) thermal annealing at 600 ~ 800 = ° C is in-situ interrogated by high-temperature scanning tunneling microscopy (STM) on a nanometer scale. The reaction is initiated by the creation of circular voids which expose the underlying silicon substrate. Growth kinetics of the voids is scrutinized via time-lapse STM movie. It shows that the minimal observable void diameter is less than 5nm and the void perimeters grow linearly with time before coalescence. Furthermore, the reaction occurs peripherally at the void perimeter. We demonstrate that the decomposition rate varies concomitantly with the local environment near the reaction fronts. The observed low-high-low rate evolution is qualitatively analyzed. An increased reaction activation energy is found in the final decomposition stage and the local morphological origin of this increase is discussed in detail. Finally the thermal coupling between the tip and sample is briefly explored. Acknowledgement: This work is in part supported by Research Grants Council of Hong Kong, particularly, through Grant Nos. CUHK4121/05E and CUHK4172/06E

4:45 PM C1-S4.3
Floating Polysilicon Wing Spacer Structure to Improve Erase Performance of NAND Flash Memory. (#150) Jung-Chan Lee, Samsung, Republic of Korea.

We study highly efficient NAND flash memory cell structure in view of erase margin. As semiconductor chips are scaled down for ultra high integration of NAND flash device, the distance between floating polysilicon gates (FG) decreases and the coupling in a direction of bit line increases, resulting in wider cell threshold voltage (Vth) distribution. Recessing the field region is known as one of feasible methods to suppress FG coupling through shielding effect of control polysilicon gate (CG). This method would improve cell Vth distribution, but erase characteristics of NAND flash devices could be aggravated due to the enhanced electric field around the edge of active region by CG. The weaker erase margin can induce the problems in NAND flash cell characteristics such as read retention and interference. Through the high temperature retention, we can restore the cell characteristics which are worsen. The ease margin could be improved fully under condition of above 350? baking for 2-hour. Since the trapped electron can be detrapped from the oxide film under the condition of 250? baking for 2 hours in general and the nitride film have much more electron trap sites than the oxide film, this result could explain clearly that most electrons are trapped in the nitride film rather than the oxide film. From the result of the field recess test, we suggest that the electrons trapped in the nitride film of ONO layers can aggravate NAND cell erase margin and this model can explain the trade-off between cell Vth distribution and erase margin. Based on this model, we developed a new NAND cell structure with an oxide wing spacer around FG , which could improve erase margin through suppressing the trapping of electrons in the nitride layer without worsening cell coupling in a direction of BL increment

C1-S5.1
Parameter Extraction for Silicon-on-Sapphire MOSFETs by using Inverse Modelling of Capacitance Measurements. (#772) Karl Bertling¹, Hiroshi Domyo², Young Tai Kim³, Tran Ho³, Aleksandar D. Rakić¹, Yew-Tong Yeow¹; ¹School of Information Technology and Electrical Engineering, The University of Queensland, Brisbane, Australia ; ²Peregrine Semiconductor Corporation, USA ; ³Peregrine Semiconductor Australia, Australia.

The dopant profile of a modern MOSFET has a significant impact on the device performance. Typically the profile is designed to achieve some specific electrical characteristics in the transistor. The final profile in the actual device is a result of a series of device fabrication processes. This is particularly so when the device parameters dimensions are small. Due to the lack of precision in the control of the fabrication processes this final profile may not be the desired design profile. It is therefore important to measure the actual profile in the device and correlate it with the measured characteristics. The fabrication process can then be adjusted to better approach the desired profile and electrical characteristics. The measurement of dopant profile is conventionally carried out on large size test structures using either electrical measurement (such as p-n junction capacitance) or by physical measurement (such as secondary ion mass spectroscopy). These measurements however do not accurately reflect the profile in small size devices. More recently inverse modelling of specific measured electrical parameters as a function a number of controlling electrical inputs is used determine the profile of the device directly. In this paper we investigate the use of inverse modelling technique to extract the dopant profile of thin film silicon-on-sapphire MOSFET's (SOSMOSFET's). Because of the isolated transistor substrate there is one less adjustable electrical input that can be used in the measurement process. Under these circumstances the gate-to-source/drain capacitance as a function of gate bias is the most suitable measured parameter for inverse modelling. 2D device modelling is used to study the sensitivity of the inverse modelling process to physical parameters of devices such as film thickness and quality of the back silicon-sapphire interface. Dopant profile of the isolated SOSMOSFET substrate extracted from experimental gate-to-source/drain capacitance will also be presented to demonstrate the efficacy of the proposed inverse modelling scheme.

C1-S5.2
Origin of the Low Frequency Type CV Curve in Silicon-on-Sapphire MOS Capacitors. (#770) Hiroshi Domyo¹, Karl Bertling², Tran Ho³, Neal Kistler¹, George Imthurn¹, Michael Stuber¹, Aleksandar D. Rakić², Yew-Tong Yeow²; ¹Peregrine Semiconductor Corporation, USA ; ²School of Information Technology and Electrical Engineering, The University of Queensland, Brisbane, Australia ; ³Peregrine Semiconductor Australia, Australia.

MOS capacitor C-V measurement is a standard tool for the investigation of the electrical properties of the gate oxide to silicon substrate of MOS devices. The theory assumes that the MOS depletion width is small compared to the thickness of the silicon substrate. In thin film silicon-on-sapphire technology the thickness of the silicon film is of the same order as the depletion width of the MOS structure such that when fully depleted the measured capacitance will include the effects of the properties of the back silicon-sapphire interface. In this paper we present experimental and simulation data to demonstrate the use of a special MOS test structure which has both majority and minority carrier contacts to the isolated thin MOS substrate. This test structure is used to study the influence of the back silicon-sapphire interface. Our experimental data show that both p- & n-doped films exhibit a back depletion layer. This implies the existence of a positive and negative charge respectively at the back interface. This model was simulated using a standard 2D device simulator and found to agree with experimental results. This charge model can be accounted for by the existence of an amphoteric trap at this interface, similar to that found in the front Si-SiO2 interface when it is subjected to hot carrier injection.

C1-S5.3
First-principles Study on Vacancy in Ge under Biaxial Strain. (#714) Jung-Hae Choi, Kwang-Duk Na, Cheol Seong Hwang, Seung-Cheol Lee, Kwang-Ryeol Lee; Korea Institute of Science and Technology, Republic of Korea.

As the scaling-down of the MOSFET continues, Ge is attractive as a channel material for the high performance device applications owing to its substantially high bulk carrier mobility relative to Si. Due to the difficulties in manufacturing the Ge wafers, the epitaxial growth of Ge on Si have been widely studied. Note that the thin Ge layer on Si substrate is under biaxial compressive strain due to its larger lattice parameter than Si. Therefore, the understanding of the defect structures in the strained condition is the fundamental step in solid state reactions including crystal growth, processing and operation of devices. Despite the rising importance of Ge and its similarities with Si, however, the intrinsic defects of Ge in strained condition are seldom characterized experimentally and theoretically. In the present study, the vacancy in Ge under biaxial strain was studied by the first principles calculations. We investigated the formation energy, relaxed structure and the electronic structure of the vacancy as a function of the magnitude and the direction of the biaxial strain. The formation energy of vacancy decreased drastically by the biaxial compressive strain and it will be discussed in terms of diffusion.

C1-S5.4
Nonvolatile Memories by using Well-Defined Ge Nanodot Layers in SiO₂ and Zr₂. (#72) Suk-Ho Choi, Department of Physics and Applied Physics, College of Electronics and Information, Kyung Hee University, Republic of Korea.

Single and multiple layers of Ge nanodots (NDs) for nonvolatile memories (NVMs) have been self-assembled at room temperature by ion beam sputtering deposition (IBSD) of ultra-small amount Ge (< 72 monolayers) between SiO2 layers without post annealing. High-resolution transmission electron microscopy demonstrates the existence of well-defined Ge ND layers with respect to the SiO2/Si interface. The absence of thermal budget during the ND formation would reduce interdiffusion of the atoms, thereby keeping the ND layer well-defined with respect to the Si/SiO2 interface and its thickness uniform. As Ge amount increases, the size of NDs increases, whilst their density decreases. Ge NDs have been also fabricated between ZrO2 layers by IBSD. Chemical composition and chemical bonding structures of the samples are investigated and controlled by using x-ray photoelectron spectroscopy and x-ray diffraction. The NVM properties are compared for metal-insulator-semiconductor structures containing Ge NDs in SiO2 and ZrO2 by measuring C-V hysteresis curves and discussed with reference to possible physical explanations.

C1-S5.5
Laplace Deep Level Transient Spectroscopy of Ultra Shallow Implanted Junctions in Si. (#704) Niki Mitromara¹, Jan Evans-Freeman¹, Ray Duffy²; ¹Research Centre for Electronic Devices and Materials, Materials and Engineering Research Institute, ACES Faculty, Sheffield Hallam University, United Kingdom ; ²NXP Semiconductors, United Kingdom.

We have carried out Deep Level Transient Spectroscopy (DLTS) and Laplace DLTS (LDLTS) measurements on very shallow implanted p-n junctions in Si. Lightly doped n-type Si was implanted with B at a dose of 5x10^15cm^-2 and energies of 5keV or 10keV, yielding B concentrations of 1x10^19cm^-3 and 3x10^19cm^-3 respectively with a range of 350nm, measured by SIMS. The10keV samples were also implanted with P, and the 5keV samples with P and As, to simulate an Ultra Shallow Junction (USJ) in an n-well. Lightly doped p-type Si was implanted with As at a dose of 6x10^15 cm^-2 and an energy of 10keV, yielding a dopant concentration of approximately 3x10^20 cm^-3 and a range of 370nm. These samples were also implanted with B at higher energies to simulate an Ultra Shallow Junction (USJ) in a p-well. The double implants resulted in p+/n/n- and n+/p/p- structures respectively, which calculation showed had two depletion regions, one at the end of each implanted region. Therefore the electric fields in both depletion regions act in the opposite sense, and by selecting the correct bias conditions it was possible to measure DLTS from the end-of-range of different implanted regions. The carrier concentration as a function of depth, derived from capacitance-voltage measurements, yields values very close to the SIMS measurement for all samples. We were able to measure carrier concentrations just tens of nanometres away from the buried junctions inside the implanted well-like regions, which enabled us to carry out DLTS and LDLTS on the end-of-range of the shallow implants. In the n+/p diode, a spatial overlap of the implanted dopants meant that at low temperatures compensation occurred, and this was reflected in the CV measurements. Therefore a DLTS scan taken over the range 350K to 30K displayed a high temperature peak due to the end of range of the shallow As implant, together with a defect originating much deeper behind the surface observed at low temperatures. LDLTS of the defect in the end-of-range of the As implant revealed two closely spaced energy levels, indicative of a complex defect structure in this region. In the p+/n diodes DLTS was carried out in the conventional voltage configuration, (reverse bias during the sampling) or a reverse configuration to access the n/n- depletion region. In both configurations the DLTS showed a very unusual sharp hole emission peak at about 50K originating from the n-type region. This signal did not respond to a change in measurement temperature and it was not possible to construct an Arrhenius plot. Such behaviour has been reported for hole emission out of quantum wells [1], and there may be a region within this highly p-doped structure that is efficiently confining holes. The higher doped samples also exhibited a broader hole trap at higher temperatures, due to B end-of-range damage. [1] M. Gad and J.Evans-Freeman, J Appl Phys 92 (2002) 5252

C1-S5.6
Applications of Anodic Aluminum Oxide Templates in Nano-Implantation and Single Crystal Growth. (#1014) Jinghua Fang, Paul Spizziri, Alberto Cimmino, Sergey Rubanov, Steven Prawer; The University of Melbourne, Parkville, Victoria, Australia.

High quality anodic aluminium oxide (AAO) has been fabricated as both a free standing and substrate integrated nano-template. With a high aspect ratio, these structures have found various applications in the fabrication of nano-crystals, nano-dots, nano-rods, nano-wires and nano-tubes. Ways of fabricating periodic arrays using AAO templates include: ion implantation and chemical vapor deposition (CVD). Periodically ordered templates with nano-pore diameters of 20nm-200nm can be realized using an electrolytic cell. In this work, details of the template synthesis will be presented along with the characterization of fabricated materials (e.g. ion implanted arrays in silicon and single crystal nano-diamonds) using scanning electron microscopy (SEM), transmission electron microscopy (TEM), scanning probe microscopy (SPM) and micro-Raman spectroscopy.

C1-S5.10
Molecular Beam Epitaxial Growth of Si on Heavily Boron-Doped Si(111) Surface: From Initial Stages to the growth of Si Polytypes. (#335) Andreas Fissel¹, Tammo Block¹, Dirk Kühne¹, Eberhard Bugiel², Hans Jörg Osten²; ¹Information Technology Laboratory, Leibniz University of Hannover, Germany ; ²Institute of Electronic Materials and Devices, Leibniz University of Hannover, Germany.

Epitaxial growth of Si on boron-covered Si(111) has become an interesting research subject. During boron deposition the Si(111) surface structure transforms from (7x7) to (√3x√3)R30?, which is completed at ⅓ monolayer (ML) boron coverage (c_b). Above 700 ?C, this structure is transformed into a regular arrangement of boron atoms in subsurface S₅ sites just below Si adatoms in T₄ sites. As shown recently, boron acts there as a subsurfactant by a change of the growth mode towards layer-by-layer growth via nucleation of Si islands 4 MLs high. The islands are nucleated in twin position with respect to the substrate resulting in a change of Si epitaxial layer orientation. This special behavior could open the way to create miscellaneous Si crystal structures (polytypes) with modified physical properties by an artifical stacking of Si MLs in an epitaxial growth process.
Here, we report about detailed reflection high-energy electron diffraction investigations of the initial growth stages. Based on that, realization of polytypic Si structures is demonstrated for the first time by a controlled multi-step epitaxial growth process.
In our experiments, we found a new growth mode in the very initial stage associated with the unusually nucleation of Si islands of only one ML high on the very inert Si(111)(√3x√3)R30? surface. During further deposition a superposition of growth via nucleation of Si islands 2 and 4 MLs high at c_b < ⅓ ML was observed indicating the simultaneous nucleation on (7x7)-superstructure domains and nucleation associated with one ML high Si islands formed on (√3x√3)R30?-domains. At c_b ≥ ⅓ ML only growth via nucleation of 4 MLs islands was observed after the first ML was completed, however, significant surface roughening occurred at c_b > ½ ML likely due to parasitic nucleation at boron clusters.
The resulting layer and substrate/layer interface structure for layers grown on Si(111) surfaces with c_b ≈ ⅓ ML were investigated by transmission electron microscopy. The Si(111)/Si-layer interface was found to exhibit the known twinning relationship, i.e. a twin boundary (TB) is formed. In a next step, structures with TBs arranged periodically along the [111]-direction and separated by only a few MLs Si were obtained by repetition of a multi-step procedure several times. This procedure consists of Si growth with defined thickness at 430 ?C, subsequent annealing at 750 ?C to induce boron surface segregation and boron deposition to stabilize the coverage between each Si growth step. In such a way, structures were obtained with a TB repeat sequence ranging from 16 MLs, corresponding to a twinning-superlattice, down to the achivable limit of 4 MLs, what is equivalent to a hexagonal 4H-Si polytype.

C1-S5.11
Rod-Like Defect Decoration with Transition Metals. (#508) Maria G. Ganchenkova¹, Vladimir A. Borodin², Risto M Nieminen¹; ¹COMP/Laboratory of Physics, Helsinki University of Technology, Espoo, Finland ; ²Russian Research Centre, Kurchatov Institute, Russian Federation.

Rod-like defects (RLDs) constitute a specific transient component of the defect microstructure, which arises in silicon samples in those processing conditions that produce large supersaturations of free interstitials (e.g. ion implantation, fast particle irradiation, oxidation). Though initially RLDs became of practical interest as interstitial sources responsible for transient enhanced diffusion of boron, in the recent years they have attracted additional interest due to their own properties, e.g. as possible luminescence centers. Another potential application might be their use as precursors of nanowires. Indeed, rod-like defects are long one-dimensional defects, which can be made conducive by e.g. decoration with metal atoms. Some recently reported experimental results on cobalt dislicide nanowire formation during the annealing of Si samples pre-irradiated with non-metal ions [1] can be straightforwardly interpreted in the framework of this idea. However, the efficiency of metal atom capture by rod like defects has not yet been addressed either theoretically, or experimentally. In this report we present the first results of ab-initio studies on the capture of transition metal atoms by interstitial chains forming 311 defects in silicon. The calculation results indicate that 311 defects are highly efficient gettering centers for metals (with the binding energies of several electron-Volts). Possible applications of the metal gettering effect by rod-like defects are discussed. [1] Ch. Akhmadaliev, L. Bischoff, B. Schmidt, Mat. Sci. Eng. C, 26 (2006) 818.

C1-S5.12
The Effect of Doping Type and Concentration on Optical Absorption via Implantation Induced Defects in Silicon-on-Insulator Waveguides. (#636) Russell Gwilliam¹, Andrew Knights², Matthew Halsall³; ¹Surrey Ion Beam Centre, Nodus Lab, University of Surrey, Guildford, United Kingdom ; ²McMaster University, Hamilton, Ontario, Canada ; ³University of Manchester, United Kingdom.

Understanding the effects of ion implantation damage of the propagation of sub-bandgap photons within a silicon waveguide is increasingly important. Defect mediated processes have been shown to be useful in silicon photonic circuits for a range of applications such as optical detection, carrier lifetime control, and in the reduction of optical cross-talk. In this work we describe the influence of the background doping type and concentration on the optical cross-section of defects deliberately introduced via ion implantation, for wavelengths around 1550nm. We show that depending upon the charge state of the defect, a significant variation in absorption can be induced, primarily dependent upon the energy level of the defect state. The implications of this phenomenon for highly integrated photonic circuits are discussed, and potential applications in the form of optical modulation are described.

C1-S5.13
Photo-detector of Silicon Nano-pillar. (#572) Shu-Fen Hu, Department of Physics, National Taiwan Normal University, Taipei, Taiwan.

A device is composed of triple quantum dots sandwiched between electrodes and is highly sensitive to the surrounding electrostatic environment. We show that the photoelectric effect resulting from the capture of photo-excited carriers by quantum dots produces a detectable change in the source-drain resistance of the transistor. Current-voltage characteristics measured at room temperature as a function of source-drain bias for sample device 1 under dark and various intensities of s 580nm illumination. The photocurrent increased as the illumination intensity increased. The dark current shows quasilinear characteristics. The photo currents were measured under the 580nm illuminations. Dramatically an increase in the measured current is observed across the entire bias range. Moreover, the measured current under manually chopped 580nm illumination, where the illumination was switched on or off at 5 second intervals during the bias sweep. The observed I-V characteristics clearly exhibit almost complete recovery of the device after illumination is removed. We have demonstrated photoconductive detectors can inherently be quite efficient, since the photo carriers are produced by band-to-band absorption in a indirect band gap semiconductor.

C1-S5.14
Radiolysis of Quartz Nano-Inclusions in Silicon Single Crystals. (#262) Elvira Memet Ibragimova, Makhmud Umar Kalanov, Rakhima Nurmat Khamraeva, Vasilya Mamat Rustamova; Radiation Solid State Physics Department, Institute of Nuclear Physics, Ulugbek, Uzbekistan.

Radiolysis of quartz nano-inclusions in silicon single crystals due to irradiation with fast neutrons has been studied. Objects were p-Si single crystals of {111} cut, with the specific resistance of 1-10 Ohmxcm, dislocation density 10-1000 cm-2, oxygen concentration up to 4x10to17 cm-3 and for boron 3x10to15 cm-3. Structure measurements were done at X-ray diffraction meter DRON-3M with the copper radiation 0.1542 nm at 300 K. Specific resistance was measured by the four-probe techniques. The samples were irradiated in the core of reactor of WWR-SM type at the Institute up to the dose of 10to20 cm-2 at 350 K. Five selective reflections occurred in the diffraction spectra of the non-irradiated samples. Analysis has shown that three of them (111) with d / n = 0.3136 nm at ~ 28.5 grad., it's betha-component and (222) with d / n = 0.1568 nm at ~ 59 grad. belong to the silicon matrix lattice. Reflection (111) has a singlet shape. Ratio of I(222) / I(111) = 0.0008. These facts are indicative of non-homogeneous oxygen distribution over interstitial positions of silicon lattice and evident to formation of quartz nano-inclusions in the defect regions of the matrix. Other two weak structure lines with d / n = 0.3345 nm at ~ 26.6 grad. and 0.2468 nm at ~ 36.6 grad. correspond to diffraction reflections (101) and (110) from the quartz crystal lattice. An average size of these quartz inclusions is about 4 nm. The X-ray-diffraction patterns of the fast neutron irradiated samples comprised only those three reflections from the silicon matrix lattice, however no reflex from the quartz nano-inclusions occurred. The dominating reflection (111) had the doublet form characteristic of two lines of copper alpha-radiation. Besides, the ratio of I(222) / I(111) = 0.0001 decreased, that evidenced on significant lowering of the mechanical stresses, which had related to the quartz nano-inclusions. These changes can be caused to radiolysis and dissolution of the quartz nano- inclusions followed by production of the point defect (oxygen and silicon interstitials) statistically distributed over the matrix lattice, which do not influence on the matrix reflection intensities. It has resulted in the crucial growth ~ 10000 times of the initial specific resistance of the non-irradiated samples. The work is supported by the national grant PFI-F068.

C1-S5.15
Method for Fabricating Uniform Porous Silicon via Pulsed Anodisation. (#951) Timothy Denis James, Adrian Keating, Gia Parish, Charles Musca; Microelectronics Research Group, School of Electrical Electronic and Computer Engineering, The University of Western Australia, Australia.

The renewed interest in porous silicon (pSi) was sparked by the discovery of light emission from pSi by Canham in the early 1990's. During the 1990's research into development of pSi components moved from light emitting devices towards optical components such as antireflection coatings, multilayer mirror stacks and refractive index graded filters. These devices are made possible due to the wide range of refractive indices achievable in pSi structures of varying porosity, and the relative simplicity of fabrication of pSi optical components. The formation of pSi is typically carried out in a single-tank PTFE electrochemical cell, in which a noble metal electrode acts as the cathode and a crystalline silicon wafer as the anode using a solution of HF/ethanol as an electrolyte. The silicon wafer is then anodised to produce layers of pSi, usually by applying a DC current to the cell. This has proven to be quite successful for creating uniform pSi thin films on heavily doped silicon starting wafers. However, the aim of this work is produce transmissive pSi/silicon based optical devices for shortwave infrared fixed filter spectroscopy, which requires low-doped silicon starting wafers. The fabrication of pSi on low-doped wafers with DC current produces pSi thin films with a porosity gradient, which results in an unwanted refractive index gradient in the film. This greatly reduces the quality of devices that can be fabricated on low-doped silicon wafers. A number of researchers have studied the affect of pulsed anodisation on pSi, yet they have only focused on luminescence, anodisation rate and morphology. The work presented will focus on the change in refractive index gradient of the pSi thin films created on low-doped silicon starting wafers. The samples are fabricated with a current pulse train, where a set of frequencies (0.1 Hz, 1 Hz and 10Hz) was used with varying duty cycles. The preliminary results show a strong dependence of porosity/refractive index on the duty cycle of the current pulse train. Samples anodized under DC conditions have a linear refractive index gradient of ?n = 0.24 through a single thin film of approximately 900nm, while a sample anodized with a 0.1 Hz pulse train with a duty cycle of 10% produced a pSi layer with zero refractive index gradient. A discussion of the mechanism behind the improved pSi thin film uniformity will be presented.

C1-S5.16
Double Boundary Trench Isolation Effects on a Stacked Gradient Homojunction Photodiode Array. (#1335) Paul Vernon Jansz, Steven Hinckley; Edith Cowan University, Australia.

CMOS photodiode (PD) array crosstalk and quantum efficiency need to be optimized to produce high-speed high-resolution imaging systems. Backwall illumination (BW), rather than frontwall illumination (FW), allows the spectral response of individual photodiodes to be tailored to a specific wavelength band, because the depth of carrier photogeneration is proportional to the wavelength due to the indirect nature of the silicon absorption coefficient. Therefore comparing the response of both illumination modes is of interest. Previous simulations of PD array response have demonstrated excellent crosstalk suppression, while sacrificing their maximum quantum efficiency, especially for the BW mode. Furthering the research of Dierickx & Bogaerts, the stacked gradient homojunction PD (StaG PD) demonstrated superior quantum efficiency and reduced crosstalk compared to PDs previously simulated. However, for increasing pixel thickness, crosstalk increased and maximum quantum efficiency reduced, especially for the BW mode. In this paper, the effect of the width, spacing and height of a Double Boundary Trench Isolation (DBTI), that straddles the interpixel boundary, on the response resolution of a two dimensional CMOS compatible photodiode array that has a stacked gradient homojunction (StaG) architecture, was simulated. Results were compared with a range of PD geometries previously simulated including the guard-ring electrode, guard-ring electrode with BTI, the StaG PD with and without inter-pixel nested ridges, StaG with BTI and the Double junction PD. Both modes of illumination showed superior response compared to all other PD geometries. Crosstalk carriers are trapped between the DBTI reducing crosstalk while the BTI in the pixel volume acts together with the StaG geometry as minority carrier mirrors reflecting photo carriers towards the depletion region resulting in superior quantum efficiency.

C1-S5.17
Modeling of Optical Properties in Silicon Nanocrystals. (#1161) Farshid Karbassian¹, Hasan Ghafoorifard¹, Shams Mohajerzadeh²; ¹School of Electrical Engineering, Tehran Polytechnic, Iran ; ²School of Electrical Engineering and Computer Engineering, Tehran Polytechnic, Iran.

Silicon, the mainstay semiconductor in microelectronic circuitry, is not suitable optoelectronic devices due to its indirect bandgap. Strong photoluminescence of chemically made porous silicon [1] shed light on silicon-based light emitting devices and silicon nanostructures were shown to be promising material for optoelectronic applications. Several methods have been reported for fabrication of silicon nanocrystals like hydrogenation of amorphous silicon, and silicon implantation in SiO2 matrix. While fabrication of silicon nanostructures has been extensively studied, the origin of their luminescence capability is still the subject of controversy. Different phenomena are believed to be responsible for light emission in silicon nanostructures. Quantum confinement [2], surface passivants such as fluorine, chlorine, oxygen and hydrogen [3], and surface defects as centers for carrier localization [4] are the most referred ones, but each has some inconsistencies with experimental results. In this manuscript a model based on solving of Schr?dinger equation in quantum dots is proposed for light emission in silicon nanocrystals. A spherical shape is assumed for silicon nanocrystals. The potential is also assumed to be spherical and the Bessel's function for electrons and holes are used to promote the energy levels in quantum dots compared to bulk silicon. Experimental results show the validity of the proposed model. References: 1. L. T. Canham Appl. Phys. Lett., Vol. 57, No. 10, pp. 1046-1048, (1990). 2. J. Heitmann, et al., Phys. Rev. B, Vol. 69, No. 19, 195309, (2004). 3. Y. Dai, et al., Solid State Commun., Vol. 126, pp. 103-106, (2003). 4. S. M. Prokes, et al., J. Appl. Phys., Vol. 73, No. 1, pp. 407-413, (1993).

C1-S5.19
Surface Roughness Engineering for Si-Based MSM Photodetector Applications. (#26) Mohd Zaki Bin Mohd Yusoff, MD Roslan Hashim; NOR LAB, School of Physics, Univesiti Sains Malaysia, Penang, Malaysia.

The application of cryogenic temperature treatment (77K) at various cooling times (15-60 minute) has been shown to significantly modify surface properties of n type silicon (100). The surface roughness of the untreated and treated samples was obtained using AFM techniques. Treated Si sample have better surface uniformity than untreated sample. The PL and Raman spectroscopy are used to describe the effect of the treatment on their optical properties. The nickel (Ni) metal contacts were then deposited on the samples followed by current-voltage characterization (I-V). Treated samples showed significantly decreased dark and light currents compared with untreated sample. Current gain (ratio of photo to dark current) of some of the treated sample is enhanced while some are reduced compared with that of untreated sample.

C1-S5.20
Schottky Barrier Height Enhancement of n-Si (100) by Temperature Treatment for Photodetector Application. (#27) Mohd Zaki Bin Mohd Yusoff, NOR LAB, School of Physics, Univesiti Sains Malaysia, Penang, Malaysia.

We have demostrated the method to modify the current response of n-type silicon photodetector. The current is modified through application of ultra-cooling temperature treatment (77K) has been proven to significantly modifying a surface properties of n-type silicon (100). The contact metal of nickel (Ni) were deposited at room temperature and characterized. The application of temperature treatment to the sample at various cooling times (15-60 minute) was investigated. Electrical and morphological characterization was performed by current-voltage (I-V) and atomic force microscopy (AFM) measurements, respectively. Treated Si sample have better surface uniformity than untreated sample and their current response decreased compared untreated sample. FTIR spectroscopy measurement shows that the formation of Si-O-Si and Si-N in both in energy and intensity in the resultant spectra indicates no a reliable passivation of the exposed surfaces

C1-S5.21
Fabrication and Electrical Properties of SrBi₂Ta₂O₉ Thin Films on Si(100) using LaZrO_x Buffer Layer for the 1T-type FeRAMs. (#213) Byung-Eun Park, Jong-Hyun Im, Ho-Seung Jeon, Chul-Ju Kim; University of Seoul, Republic of Korea.

The Metal-ferroelectric-semiconductor (MFS) structure has superior advantages such as high density integration and non-destructive read-out operation. However, to obtain the desired electrical characteristics of an MFS structure is difficult because of interfacial reactions between ferroelectric thin film and Si substrate. As an alternative solution, the MFS structure with buffer insulating layer, i.e. metal-ferroelectric-insulator-semiconductor (MFIS), has been proposed to improve the interfacial properties. In this study, we inserted the sol-gel derived LaZrOx (LZO) buffer layer as an intermediate insulator between the SrBi2Ta2O9 (SBT) thin film and Si substrate to form an MFIS structure. To form a LZO buffer layer, the LZO solution was spin-coated on Si at 4000 rpm for 25 seconds. Then The LZO thin film was annealed at 750 ? for 30 minutes in O2. Subsequently, SBT solution was spin-coated on LZO/Si at 3000 rpm for 20 seconds and dried on hot plate at 250 ? for 10 minutes. After these processes were repeated to obtain the desired thickness, SBT film was finally crystallized at 800 ? for 30 minutes in O2. We observed the surface morphology and crystallization quality of films using atomic force microscopy (AFM) and x-ray diffractometer (XRD), respectively. To evaluate electrical properties, the capacitance-voltage (C-V) and current density-voltage (J-V) characteristics of Au/SBT/LZO/Si structure were measured. From the C-V measurements, the clockwise ferroelectric hysteresis loops were observed and the memory window width became larger as the bias voltage increased ?3 V to ?7 V. The memory window width was about 1.2 V for the bias voltage of ?7 V. The leakage current density of the structure was lower than 1.0x10-6 A/cm2 at 10 V.

C1-S5.22
Fabrication and Electrical Properties of Sol-Gel Derived High-k Dielectric Lanthanum Zirconium Oxide Thin Films. (#1034) Byung-Eun Park, Ho-Seung Jeon, Jong-Hyun Im, Chul-Ju Kim; University of Seoul, Republic of Korea.

The continued scaling down in dimension of complementary metal-oxide-semiconductor devices has pushed the thickness of the gate dielectric towards ~2 nm. However, leakage current of conventional silicon dioxide gate dielectric increases exponentially with the film thickness reduction. For this reason, alternative high-k dielectrics have attracted much attention. Here, we attempt to investigate dielectric properties of the lanthanum zirconium oxide thin films, among the available high-k dielectrics, as an alternative gate dielectric. In this experiment, lanthanum zirconium oxide thin films were prepared by the sol-gel method. The sol-gel solution was synthesized with different ratios of La/Zr in order to vary the film composition ratio. Such sol-gel prepared lanthanum zirconium oxide thin films were annealed in flowing oxygen at different temperatures from 600 to 800 ?C. For electrical measurement, Pt top electrodes with a diameter 0.2 mm were sputtered. In the same way, lanthanum zirconium oxide thin films were also prepared on a Si substrates. But surface-treatment for Si substrates was performed before film deposition. These thin films have been characterized using differential thermal analysis (DTA), thermogravimetric analysis (TGA), X-ray diffraction (XRD), scanning electron microscopy (SEM), Auger spectra (AES), and electrical and dielectric measurements. In particular, high-frequency capacitance-voltage measurements revealed that films of La/Zr=1 annealed at 750 ?C had good dielectric properties with negligibly small hysteresis voltages. Its relative permittivity was around 12 ~ 18.

C1-S5.23
Characterization of Interface States in PtSi/p-Si Schottky Diodes Using Admittance Technique. (#805) Azzouz Sellai, Department of Physics, Sultan Qaboos University, Oman.

PtSi-p/Si Schottky diodes have been used as photodetectors in the infrared region due essentially to their low barrier heights, response uniformity and compatibility with monolithic integrated silicon technology. The cut-off wavelength is directly related to the Schottky barrier height which is known to depend on interface states and temperature [1-5]. We have, in this context, investigated the interface properties of PtSi-p/Si Schottky contacts using admittance measurements over the frequency range 1kHz - 1 MHz at different temperatures between 80 K and 200 K. The 0.64 mm2 test diodes were prepared using conventional Pt evaporation followed by annealing in situ. The measured excess capacitance at lower frequencies is seen as a signature for the presence of interface states. The densities (Dit) of these states are found to be slightly temperature- as well as voltage-dependent with an average value estimated to be around 6x1012 eV-1cm-2. The presence of interface states is also evidenced as a peak manifest at all temperatures in the Gss/&omega-&omega plots. Gss is the conductance due to interface states which was derived from the measured capacitance and conductance [6]. Css and Gss are particularly related to the interface states density and the relaxation time (&tau) of these states which is associated with the capture cross section (&sigma). Analytical expressions for Gss as a function of Dit and &tau could be derived in two special cases corresponding to the respective situations of an energy-dependent &sigma and Dit having a maximum influence on Yss=Gss + j&omegaCss, or a constant cross section and constant density within an energy range of a few kT. The fit of experimental data was not very good in the latter case which may insinuate that the assumption of a density of states and a capture cross section not varying with energy over a few kT is not valid. Despite a noticeable discrepancy at very low frequencies and at low temperatures in particular, a better fit could be achieved assuming an energy dependent s and Dit. In fact, the fit is particularly excellent around the peak region and for frequencies beyond, suggesting that the interface states density and relaxation times are to some extent energy dependent. The conductance data is subsequently used to extract the relaxation times of interface states and their energy distribution with respect to the top of the valence band. Relaxation times of the order of 4 micro-seconds were obtained at 100K and although they show some temperature dependence they are practically independent of bias. 1- A. Sellai, P. Dawson, Nuclear Instrumentation and Methods (NIM-A) vol. A567 p.372 ((2006) 2- P.G. McCafferty, A. Sellai, P. Dawson and H. Elabd, Solid State Electronics, vol. 39, p. 583 (1996) 3- M. Mamor et al. J. Phys. D: Appl. Phys., vol. 40 p. 1351 (2007) 4- A. Sellai and M. Mamor, Appl. Phys. A, vol. 89 p. 503 (2007) 5- A. Sellai, M. Mamor and S. Al-Harthi, Surface Review & Letters, vol. 14 p. 765 (2007) 6- J. Werner, K. Ploog and H.J. Queisser, Phys. Rev. Lett., vol. 57 p. 1080 (1986)

C1-S5.24
Pressure-Induced Phase Transitions in Semiconductors. (#182) Varghese Swamy, Department of Materials Engineering, Monash University, Victoria, Australia.

Pressure-induced phase transitions in semiconductors have attracted significant attention from the fundamental and technological viewpoints. The pressure-dependent phase transitions of silicon, in particular, have been the subject of extensive experimental and theoretical investigations. The pressure-induced phase transitions can lead to metallization of (the usually semiconducting) ambient pressure diamond-structured Si or to amorphization and polyamorphic transitions depending on the nature of the starting material and the pressure-temperature combination employed. The effects of physical size reduction on the phase transition behaviour of silicon have attracted significant interest in recent years. The polymorphism and amorphization in silicon-type materials have great implications for the functionalities and applications in a range of technologies. This presentation will summarize the current state of knowledge with regard to pressure- and size-dependent phase transitions in prominent semiconductors and the implications to observed phenomena in nanoindentation, thin-films, and other related areas.

C1-S5.25
An Angular Dependence Deep-level Transient Spectroscopy Study of He Implanted Si. (#738) Byron John Villis, Jeffrey C McCallum; The University of Melbourne, Parkville, Victoria, Australia.

Ion implantation is the most common way to reproducibly incorporate dopant atoms into Si wafers. As the dimensions of Si devices shrink, the use of lower implantation energies is increasingly important in the fabrication of these devices. However by using a low implantation energy, channelling of the incident ion through the Si lattice becomes increasingly probable. This effect is often undesirable as it significantly alters the ion range and other important implantation parameters. As a consequence, a surface scattering oxide is often used to prevent channelling. It is not always convenient however, to fabricate this oxide nor is the effectiveness of the oxide well understood in the light ion, low energy limit. For these reasons it is desirable to develop an accurate model of the ion channelling effects. There are several simulation programs based on the Monte Carlo approximation which are able to predict the channelled implant profiles in crystalline Si, namely Crystal-TRIM and MARLOWE. However, these codes have not been fully tested for the low dose, light ion limit since much of the experimental data used to validate these codes required a high implanted fluence for the ion range and damage accumulation profiles to be accurately measured. Here, we present a Deep-Level Transient Spectroscopy (DLTS) measurement of electrically active charge traps created by the implantation of 400 keV He at various implantation angles. He ions were chosen as they are relatively easy to channel at these energies and the depth range can be directly probed by DLTS. DLTS is particularly suited to this type of study since it is able to accurately measure and distinguish very low defect concentration in Si with minimal processing steps. In addition to measuring the defect concentrations, by slightly modifying this technique DLTS also provides a means to accurately profile the depth over which a particular defect exists (Double correlation DLTS). Initially the substrates where orientate to the [100] axis using Rutherford Backscattering (RBS) and ion channelling with a focused 400 keV He+ beam produced by the University of Melbourne Pelletron. The He+ beam was then defocused and scanned across the wafer surface to perform the He implantation at the desired implantation angle. The implantation was performed through a variety of surface layers including Hydrogen-terminated surfaces, created using a HF, alcohol and H2O solution, native oxides and low defect purpose-grown surface oxides, grown in a triple walled furnace. The defect depth profiles measured here have been directly compared to the vacancy profile simulated in Crystal-TRIM. With the results presented here, a clear understanding of how channelling influences defect depth profiles created by 400 keV He in Si at various angles to the [100] axis. This study also sheds light on the effect of surface oxides on the scattering of incident ions. These results have far reaching implications for the semiconductor industry.

C1-S5.26
Investigation of SOI Materials Fabricated by Etch Stop Thinning Process. (#156) Xing Wei, Miao Zhang, Meng Chen, Xi Wang; Shanghai Institute of Microsystem and Information Technology, China.

Instead of the conventional bonding and etching back SOI (BESOI), this paper presents the investigation on the SOI materials fabricated by etch stop thinning process. The etch stop layers were formed by oxygen implantation caused oxidation inside device silicon wafers, which were bonded to handle wafers afterwards. An alternative approach is to bond an epitaxial wafer to a handle wafer and utilize the transition between the heavily doped Epi substrate and the lightly doped Epi layer as an etch stop. The etch stop thinning process was expected to generate a device layer (DL) of SOI microstructure with tight thickness tolerance. The formed SOI materials were characterized by spectroscopic ellipsometer (SE), cross-sectional transmission electron microscopy (XTEM) and atomic force microscopy (AFM) for thickness uniformity, microstructure and surface morphology, respectively. SE measurement indicated that SOI materials with excellent thickness uniformity of ?5 nm at DL thickness of 130 nm were formed by the etch stop thinning process. In addition, atomic scale sharp interface between DL and the buried oxide (BOX) layer was observed by XTEM study. However, by AFM, square micro-pit morphology was found on some SOI surface. It was deduced that the square pit defects had been formed during TMAH anisotropic etching of the SOI film through the etch stop layer. The oxygen implantation caused oxidation was responsible for such a non-stop etch behavior. Focus ion beam (FIB) analysis on the implanted area has confirmed the finding. By optimization of the implantation parameters and the high temperature annealing process afterwards, the etch stop could be completely accomplished. The feasibility to fabricate advanced SOI materials by etch stop thinning process has been demonstrated.

11:00 AM *C2-S2.1 (invited)
Combined Super STEM, and PL Spectroscopy of Un-Doped and Rare Earth Doped nc-Si-rich SiO_x and SiN_x Thin Films on (100) Si. (#329) Matthew Peter Halsall¹, Iain Crowe¹, Tyler Roschuk², Ben Sherliker¹, Ursel Bangert¹, Andrew Knights², Peter Mascher²; ¹School of Electrical and Electronic Engineering, The University of Manchester, United Kingdom ; ²McMaster University, Hamilton, Ontario, Canada.

Recently reported works on narrow (< kBT) luminescence line-widths from single silicon nanocrystals[1] have opened up the possibility of developing silicon based quantum dot devices as alternatives to those based on conventional III-V systems. In this article we explore the origin of the luminescence from nano-crystalline silicon (nc-Si) embedded in a SiOx (or SiNx) matrix and relate it to that observed in etched Si pillar structures. SiOx (or SiNx) layers were deposited via PECVD (electron cyclotron resonance or inductively coupled plasma) onto Si (100) substrates and subsequently annealed invoking phase segregation between Si-rich and SiO2 (or Silicon nitride) rich phases. Subsequently, silicon nano-clusters in the range, 3 to 5nm in diameter are formed within the dielectric Silicon dioxide (or Silicon Nitride) layer. The quantised atomic like energy level transitions in these nano crystals correspond to wavelengths in the visible to near infrared part of the spectrum (~0.7 to 0.8microns) depending on co-doping gas. Some samples, doped with Er during the deposition process, yield an add itional emission line around 1.55microns corresponding to the transition of carriers between the 4 I 13/2 and the 4 I1 5/2 energy levels of the Er3+ ion. The PL intensity of this line was found to be dependent on the anneal temperature, co-doping gas and flow pressure during growth. Time and temperature dependence of the photoluminescence spectra is presented. The nano-structures were studied using combined aberration corrected Scanning Transmission Electron Microscopy (STEM) and Electron Energy Loss Spectroscopy (EELS) to analyze the composition and structure on the nm scale. The EELS data from cross sections through nanocrystals show that the nanocrystals are composed of a gradation of increasingly silicon rich oxide up to crystalline silicon as one moves across the oxide-nc interface. Arrays of silicon nanocrystals were also prepared by formation of silicon pillars using lithography followed by gradual oxidation until a single silicon nanocrystal remains in each pillar. We discuss the luminescence observed from such single pillars using micro photoluminescence and how this relates to the macroscopic photoluminescence from layers containing ensembles of nanocrystals. We conclude that this system has potential for realising a range of photonic devices based on silicon.

11:30 AM C2-S2.2
Silicon Oxide-Embedded Silicon Nanocyrstallites Prepared by Phase-Separation of Silicon-Rich Silicon Oxide. (#237) Chun K. Wong, Hei Wong; Department of Electronic Engineering, City University of Hong Kong, Hong Kong.

Silicon microelectronic technology is now developing into the nanoscale range. The material properties in the atomic scale differ dramatically from those of the bulk materials. On one hand, this trend imposes constraints on the further downsizing of microelectronic devices, but on the other hand it opens up diverse potential applications for quantum device structures. One of such applications is the microelectronics-photonics integration. It has been proposed that using Si-based materials and microfabrication technology would be a promising technology for integrated photonics. Recent efforts further demonstrated that strong light-emitting is possible in low-dimensional silicon materials. One of the promising materials is the SiO2-embedded Si nanocrystallites (Si-nc). This material shows stable and strong photoluminescence (PL) characteristics. This work reports a new method for preparing SiO2-embedded Si-nc by high-temperature annealing of Si-rich SiO2. Various characteristics of these materials are studied in detail. Si 2p XPS spectra of as-deposited samples exhibits only a single near symmetric peak which is attributed to the random bonding Si4-nOn (n = 0, 1, 2, 3 or 4) tetrahedral. As the annealing temperature increases, the Si 2p peaks shift to low energy side. It indicates that the Si atoms in the annealed samples appear in larger oxidation states and the films tend to be more stoichiometric. The Si 2p spectra of films annealed at above 1000 °C manifest a double-peak structure. Gaussian deconvolution of the peak indicates that the contributions of Si+, Si2+ and Si3+ components become smaller, while the contributions of Si4+ and Si0 components are more dominant. This suggests that the unstable sub-oxides have been converted into more stable Si-Si4 and Si-O4 phases. This phase-separation effect is insignificant in samples deposited with larger flow ratio as the oxide film is essentially stoichiometric oxide. The Raman peak found at around 516 cm^-1, corresponding to the transverse optical (TO) mode of Si-nc also confirms the formation of Si-nc. The red-shift and broadening of the TO peak at higher annealing temperatures can be attributed to the photon confinement effects. The as-grown samples demonstrate a broad PL peak in the range of 600 to 700 nm. The red PL can be enhanced pronouncedly by increasing the annealing temperature. This observation can be explained by the growth of Si-nc size during annealing. The high temperature annealing of Si-rich oxide films has two consequences: (1) formation of Si nanocrystallites due to the phase-separation effect; (2) removal of Si dangling bonds, hydrogen bonds, and other defect states. Both effects would lead to stronger PL peak due to quantum confinement. TEM pictures clearly indicate that the even distribution of Si nanocrystallites in the annealed samples. Direct correlation among the crystallites size with PL peak energy was found.

11:45 AM C2-S2.3
Influence of Matrix Properties on Luminescence Related to Ion-Synthesized Si Nanoclusters. (#401) David Tetelbaum¹, Alexey Mikhaylov¹, Alexey Belov¹, Yulia Mendeleva¹, Alexey Ershov¹, Alexandr Kasatkin¹, Oleg Gorshkov¹, Anatoly Kovalev², Dmitry Wainstein², Rasit Turan³, Terje Finstad⁴; ¹Physico-Technical Research Institute of University of Nizhny Novgorod, Russian Federation ; ²Surface Phenomena Research Group, Russian Federation ; ³Middle East Technical University, Ankara, Turkey ; ⁴University of Oslo, Norway.

Ion-beam synthesis is one of the most suitable methods for fabrication of light-emitting layers of silicon nanocrystals / nanoclusters (nc-Si) embedded into wide-band matrices. A majority of works have been devoted to studying the SiO2:nc-Si system, whereas progress in nano- and optoelectronics demands diversification of the matrix materials. Some publications on Si nanocrystals in other than SiO2 dielectrics appeared last years. However, the preparation conditions, which are not identical in various works, complicate establishment of general regularities determining the properties of the systems. In the report, the comparative investigation of the photoluminescence (PL) of several layers with ion-synthesized nc-Si is presented. The matrix materials include SiO2/silicon, GeO2/quartz, Si1-xGexO2/silicon, a-Al2O3/silicon, single-crystal &alpha-Al2O3 sapphire, a-Si/silicon. The nc-Si in the oxide layers were synthesized by Si+ implantation at 100-150 keV and postannealing at 500-1100 °C. The a-Si layers containing nc-Si were formed by not quite complete amorphization of silicon by ion irradiation and low-temperature postannealing (~ 300 °C). PL was excited by a nitrogen (337 nm) or argon (488 nm) lasers at room temperature. The structure was studied by the high-resolution electron microscopy, and the character of chemical bonding was investigated by the electron spectroscopy (EELFS and XPS). It is established that luminescent properties of nc-Si depends strongly both on chemical composition and the structure (depending, in turn, on the fabrication method) of the matrix. In particular, nc-Si formed in Al2O3 films give rise to PL in the same spectral range as in SiO2 (700-900 nm); on the contrary, they do not exhibit such light emission being synthesized in sapphire. The nc-Si emitting light in the pointed above range are formed well by Si implantation in the GeO2/quartz, but not so readily as in the Si1-xGexO2/quartz. In the case of the ion-irradiated Si, the PL band at 900-1000 nm related to the emission from a-Si is observed in addition to the nc-Si-related PL band at around 750 nm. The results are interpreted using the models taking into account the size correspondence of Si and matrix atoms (as for the GeO2 and Si1-xGexO2); mechanical stresses leading to breaking-up the interface bonds (as for the nc-Si in sapphire); electron exchange between Si nanocrystals and matrix (as for the a-Si:nc-Si). These results indicate certain limitations for fabrication of the light-emitting nanosystems and point out possible ways of their overcoming. The work was partially supported by the European Commission through project SEMINANO, Russian Ministry for Education and Science (RNP Programme), CRDF (BRHE Programme), and grant of the President of Russian Federation (MK-3877.2007.2).

12:00 PM C2-S2.4
Integration of Low Dimensional Crystalline Si into Functional Epitaxial Oxides for Next Generation Solar Cell Application. (#688) Apurba Laha¹, Andreas Fissel¹, Eberhard Bugiel¹, Mikhail Badylevich², Valeri Afanasiev², Hans Jörg Osten¹; ¹Information Technology Laboratory, Leibniz University of Hannover, Germany ; ²Department of Physics, University of Leuven, Belgium.

Quantum confinement of charge particles within nanostructured materials could lead to a large number of exotic phenomena, which would never been realized in normal bulk materials. For example, a typical solar cell material generates one electron per photon of incoming sunlight. However, if we reduce the size of the Si cluster into the quantum regime, it could produce two or three electrons generated from high-energy photons of the sunlight. Such effect could pave the way for new generation solar cells with ultrahigh efficiency well over 60 percent.
In this presentation, we will show that by modifying the growth kinetics during molecular beam epitaxy (MBE) one could easily create Si nanostructures of multiple dimensions, such as Si quantum dots (QDs) or quantum wells (QWs), buried into epitaxial dielectric oxide material on Si substrates. The spatial (both vertical and horizontal) distribution of Si-QDs was controlled by carefully monitoring the deposition parameters during MBE growth. The oxide used in this work was the rare earth oxide Gd₂O₃ with a dielectric constant > 15. Si-QDs of varying sizes and QWs of different width embedded into crystalline rare earth metal oxide could be a smart way to engineer the band structure of Si and could serve as multiple band gap materials in silicon based tandem cells or for hot carrier cells.
The physical properties of Si-QDs and QWs were investigated by various characterization techniques, such as reflection high-energy electron and x-ray diffraction, atomic force and transmission electron microscopy, internal photo emission (IPE) spectroscopy, capacitance-voltage and current-voltage (I-V) measurements.
The investigation of electronic structure of such Si-QDs shows, that the energy threshold of electron IPE from the Si-QDs to Gd₂O₃ is equal to 4.5 ± 0.2 eV, which is more than 1 eV higher than the threshold of electron IPE from the valence band of bulk Si crystal to the conduction band of the oxide. The optical absorption of Si-QDs with an average size of 5nm is found to exhibit a spectral threshold at 2.5 ± 0.1eV suggesting a significant quantum confinement effect. In further studies on stacks of multiple oxide layers containing Si-QDs with different sizes a broad range of spectral threshold was found indicating size dependent optical absorption in the QDs. Such interesting properties of Si-QDs in a dielectric matrix make them to a strong candidate for next generation solar cell application where the size dependent spectral response could be useful for absorption of a large part of the solar spectrum, which is almost impossible with only one semiconductor material.
Furthermore, I-V characteristic obtained for structures containing Si-QWs as well as Si-QDs exhibited negative differential resistance, making them to an attractive candidate for resonant tunneling devices and hot carrier solar cell contacts in the future.

LUNCH 12:30 PM - 2:00 PM

2:00 PM *C2-S3.1 (invited)
Alloying, Self-Ordering and Stability of Ge/Si Semiconductor Nanostructures. (#1393) Federico Rosei, Institut National de la Recherche Scientifique, Énergie, Matériaux et Télécommunications (INRS-EMT), Canada.

Exploiting growth processes and kinetic instabilities to form surface nanostructures and patterns is emerging as a key element in strategies for nanoscale fabrication. In heteroepitaxy, the strain energy caused by the lattice mismatch competes with kinetics to form nanostructured films [1-3]. Ge on Si is a model heteroepitaxial system that follows the Stranski-Krastanov growth mode [3], and is widely investigated for prospective applications in nanoelectronics and optoelectronics. Similarly to the InAs/GaAs system, it is known that Ge-Si intermixing [4-8] occurs during growth by way of a strain relief mechanism, altering the composition of the as grown QDs. Here we provide an overview of allying dynamics in Ge/Si films and nanostructures investigated using synchrotron based techniques, in particular X-Ray Absorption Fine Structure (XAFS) [5, 6] and X-Ray Photoemission Electron Microscopy (XPEEM) [7, 8]. Recent developments allowed us to map the surface concentration of individual Ge(Si) nanostructures [9], to study local ordering [10-12] and to investigate stability and alloying dynamics with respect to annealing [13].

[1] F. Rosei, J. Phys. Cond. Matt. 16, S1373 (2004).
[2] F. Rosei, R. Rosei, Surf. Sci. 500, 395 (2002).
[3] F. Ratto, G. Costantini, A. Rastelli, O.G. Schmidt, K. Kern, F. Rosei, J. Exp. Nanoscience 1, 279-305 (2006).
[4] A. Sgarlata, P.D. Szkutnik, A. Balzarotti, N. Motta, F. Rosei, Appl. Phys. Lett. 83, 4002 (2003).
[5] F. Boscherini, G. Capellini, L. Di Gaspare, F. Rosei et al., Appl. Phys. Lett. 76, 682 (2000).
[6] N. Motta, F. Boscherini, A. Sgarlata, A. Balzarotti, G. Capellini, F. Ratto, F. Rosei, Phys. Rev. B 75, 035337 (2007).
[7] F. Ratto, F. Rosei et al., Appl. Phys. Lett. 84, 4526 (2004).
[8] F. Ratto, F. Rosei et al., J. Appl. Phys. 97, 043516 (2005).
[9] F. Ratto, A. Locatelli, S. Fontana, S. Kharrazi, S. Ashtaputre, S.K. Kulkarni, S. Heun, F. Rosei, Small 2006, 2, 401-405.
[10] F. Ratto, A. Locatelli, S. Fontana, S. Kharrazi, S. Ashtaputre, S.K. Kulkarni, S. Heun, F. Rosei, Phys. Rev. Lett. 96, 096103 (2006).
[11] F. Ratto, T. W. Johnston, S. Heun, F. Rosei, Surface Science 602, 249 (2008).
[12] F. Ratto, F. Rosei, S. Heun, O. Moutanabbir, submitted.
[13] F. Ratto, F. Rosei, S. Heun, O. Moutanabbir, in preparation.

2:30 PM C2-S3.2
Structural Characteristics of Epitaxial GeSi/Si Quantum Dots During the Initial Si Capping. (#562) Yue Qin Wu¹, Fan Hua Li¹, Jian Hui Lin¹, Zui Min Jiang¹, Jin Zou²; ¹Fudan University, Shanghai, China ; ²The University of Queensland, Brisbane, Australia.

Epitaxially grown semiconductor quantum dots have many unique properties due to zero-dimensionally confinement of free electrons. Based on these properties, quantum-dots based devices, such as quantum dots lasers and single-electron transistors, have been designed and demonstrated. Ge(Si) quantum dots grown on Si wafers represent a key class of semiconductor quantum dots due to their compatibility with current Si technology. For these Ge(Si) quantum dots to be practically useful, Si needs to be capped on top of Ge(Si) quantum dots. Recently, we found that, during the initial stage of the Si capping process, the Ge(Si) quantum dots underwent a morphological change and donut shaped quantum rings can be resulted [1]. Since the physical properties of nanostructures are, in general, very sensitive to their structural characteristics (e.g. size, shape and composition), understanding the structural variation of quantum dots during the Si capping becomes critical. In this presentation, we varied the Si capping process to see the morphological change of Ge(Si) quantum dots. Through detailed structural characterisations (namely atomic force microscopy and transmission electron microscopy), we found that: (1) during the initial growth of the Si capping layer at 640C, the originally dome shaped Ge(Si) quantum dots become pyramid shaped and with increasing the thickness of the capping layer, the pyramid shape changes from {103} to {104} and terminates at {105} [2]. (2) If the Si capping is terminated when the {103} pyramid shaped quantum dots are formed, the annealing of the dots at room temperature can cause the facets change from {103} to {104}. This study indicates the {103} faceted pyramids are unstable [3]. (3) The compositional profiles in these semi-capped GeSi vary with the capping thickness [4]. (4) The low temperature (less than 350C) Si capping can preserve the Ge(Si) quantum dots in their original shape [5]. [1] J. Cui et al. Appl. Phys. Lett. 83 (2003) 2907. [2] Y. Q. Wu et al. Appl. Phys. Lett. 87 (2005) 223116. [3] Y. Q. Wu et al. Nanotech. 18 (2007) 025404. [4] F. H. Li et al. Appl. Phys. Lett. 89 (2006) 103108. [5] F. H. Li et al. Nanotech. 18 (2007) 115708.

2:45 PM C2-S3.3
Chalcogen Doping for Infrared Optoelectronic Si. (#1140) Brion Bob¹, Supakit Charnvanichborikarn², Jeffrey M. Warrender¹, Atsushi Kohno³, Malek Tabbal⁴, Jim S Williams², Dimitris Papazoglou⁵, Michael J. Aziz¹; ¹Harvard School of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts, USA ; ²Research School of Physical Sciences and Engineering, Australian National University, Australia ; ³Department of Applied Physics, Fukuoka University, Japan ; ⁴Department of Physics, American University of Beirut, Lebanon ; ⁵Materials Science and Technology Department, University of Crete and Institute of Electronic Structure and Laser, Foundation for Research and Technology-Hellas (FORTH), Greece.

Doping Si with a chalcogen in excess of the solubility limit has been shown to result in subbandgap optical absorption and sensitive photodetection. This suggests potential for chalcogen-doped Si as an infrared optoelectronic material. We investigated optical absorption and photovoltaic energy conversion using S, Se, and Te as dopants. We achieved supersaturation of the chalcogen dopant by ion implantation and pulsed laser melting and rapid solidification. The subbandgap absorption and photovoltaic response depended sensitively on the chalcogen dose, laser processing conditions, and subsequent thermal anneal. We measured the infrared absorption with UV-VIS spectroscopy and Fourier Transform Infrared Spectroscopy over a wavelength range from 1 to 11 microns. We investigated the changes to the absorption spectrum that result from varying ion implantation, laser processing, and thermal annealing conditions. We discuss these observations in light of the corresponding influence of the processing conditions on the material's crystalline quality, chalcogen dopant depth profile, carrier concentration profile, and dopant activation, which we measured with Rutherford Backscattering Spectrometry, Secondary Ion Mass Spectrometry, and Spreading Resistance Profiling, respectively. We found good agreement between the chalcogen depth profiles obtained from experiments and a 1-dimensional model for plane-front melting, solidification, liquid-phase diffusion, and kinetic solute trapping.

3:00 PM C2-S3.4
Point Defect Engineered Sub-Bandgap Si Light-Emitting Diode. (#755) Supakit Charnvanichborikarn¹, Yu Yang², Jiming Bao³, Malek Tabbal⁴, Taegon Kim³, Yin-Yin Jennifer Wong-Leung¹, Jim S Williams¹, Michael Aziz³, Federico Capasso³; ¹Electronic Materials Engineering Department, Research School of Physical Sciences and Engineering, The Australian National University, Australian Capital Territory, Australia ; ²Institute of Engineering and Technology, Yunnan University, China ; ³Harvard School of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts, USA ; ⁴Department of Physics, American University of Beirut, Lebanon.

Achieving efficient light emission from Si and the fabrication of active optical components is a major challenge as a result of the indirect bandgap of Si. We present recent results on a novel approach to sub-bandgap Si light emission from point defects that combines ion implantation, pulsed laser melting (PLM), and rapid thermal annealing (RTA) to engineer a high concentration of point defect clusters that mediate radiative recombination at a wavelength of 1218 nm, which is corresponding to W-line emission. A sub-bandgap light emitting diode exhibiting good p-n junction characteristics was fabricated. The intensity was measured to be about three orders of magnitude greater than band-edge luminescence at cryogenic temperatures. In order to optimise the luminescence, various implantation schemes and processing schemes have been investigated. For example, we have used both low dose implantation and annealing to directly produce interstitial clusters and light emission closely related to the disorder (interstitial excess) profile, and high dose implantation where interstitial clusters and light emission occurs much deeper in the material, well beyond the implantation profile. PLM and reactive ion etching (RIE) have been used to remove near-surface disorder in the latter case and RIE is additionally used for depth profiling to determine the luminescent intensity versus depth. Our recent studies conducted on 1500-nm silicon-on-insulator (SOI) reveal the most intense luminescence when the dose lies within the range of about 1E13 cm^-2 to 1E14 cm^-2 for the implantation energy of 500 keV and the strongest intensity when the etched depth is slightly beyond the ion projected range. In addition, a more uniform distribution of the intensity profile, which is an indication of the luminescence source spreading over a thicker layer, was achieved by double implantations of Si at two different energies. Thermal quenching of W-line luminescence was identified whereby the luminescence dropped dramatically above 80 K. Prospects for extending the luminescence to room temperature and for achieving laser gain will be discussed.

3:15 PM C2-S3.5
Maskless Patterned Etching of Silicon Dioxide by Inkjet Printing. (#697) Alison Joan Lennon, Anita Ho-Baillie, Stuart Wenham; School of Photovoltaic and Renewable Energy Engineering, The University of New South Wales, Sydney, Australia.

The patterned etching of silicon dioxide dielectric layers is widely used in semiconductor device fabrication to provide a mask for etching and diffusion and to facilitate metal contacts to underlying semiconductor surfaces. Typically, it is achieved using resist-based methods, where the pattern is formed in the resist using either photolithography or an inkjet device, and then the patterned resist is immersed in corrosive etching fluids containing hydrogen fluoride (HF). The resist is then removed leaving the patterned silicon dioxide as a mask for subsequent processes. In this paper we describe a method for the patterned etching of silicon dioxide that does not require a masking (resist) layer and is safer than existing immersion etching methods in that the corrosive etchant HF is only formed in-situ on the surface to be etched. Compared to existing immersion etch methods, the method reduces chemical usage and produces significantly less hazardous chemical waste. The method involves bringing together at least two inactive etching components at the surface location where etching is required. The components react in situ to form HF which then etches the underlying silicon dioxide. The first component is provided by an acidic, water-soluble polymer surface layer which is formed over the material to be etched and acts as a source of protons. The second component is an aqueous solution containing a fluoride source. It is applied to the surface, according to a predetermined etching pattern, by an inkjet printing device. At the surface, deposited droplets of the aqueous fluoride solution first locally dissolve the polymer where they contact the polymer film, and then fluoride ions abstract protons from the acidic polymer to form HF in situ. Using our method we have been able to cleanly etch grooves 70 &mum wide and 350 nm deep in silicon dioxide. These results have been achieved using a FUJIFILM Dimatix DMP printer with a 10 pL cartridge to print a 10 % (w/v) ammonium fluoride solution onto spin-coated polyacrylic acid films. We have also etched holes ~ 55 &mum in diameter in silicon dioxide using this method. However, the etching of holes slows considerably as the diameter of the opening at the bottom of the hole becomes very small. To date, our deepest holes have been 220 nm, however we are hoping that we can increase the etched depth to be at least ~ 300 nm. The method has immediate application to the formation of patterned openings in dielectric layers for metal contacts to silicon solar cells, however, it will most likely, have applications beyond solar cell manufacture. Furthermore, although our work has focussed on the patterned etching of silicon dioxide, it is possible that it may also be applied to the patterned etching of other dielectrics such as silicon nitride. Finally, the general approach of inkjetting an inactive etching component onto a receptive layer may also be able to be applied to the etching of other materials including metals and semiconductors.

AFTERNOON BREAK 3:30 PM - 4:00 PM

4:00 PM *C2-S4.1 (invited)
MEMS-based Tunable Fabry-Perot Filters on Silicon Substrates. (#880) Jason S Milne, John M Dell, Adrian J Keating, Lorenzo Faraone; School of Electrical Electronic and Computer Engineering, The University of Western Australia, Australia.

Wavelength-tunable infrared sensors have been fabricated by combining a micro-electro-mechanical systems (MEMS) optical filter with a broadband infrared photon detector. The MEMS filter is a tunable Fabry-Perot cavity consisting of a fixed mirror and a movable mirror suspended by flexible arms. The Fabry-Perot structure reflects all wavelengths of light except for a narrow band of wavelengths that cause resonance in the cavity. By changing the cavity length using a MEMS electrostatic actuator the transmitted wavelength band is can be tuned. Sweeping across a range of cavity lengths and measuring the light striking the broadband infrared detector allows the spectrum of the incident light to be measured. This work presents recent measured results and current design issues for MEMS-based filters operating in the 1.6-2.5 µm region. Working devices fabricated monolithically on HgCdTe detectors have been reported previously, however these devices were unable to tune over the complete range of desired wavelengths, and were susceptible to rapid performance degradation. The limited tuning range in previously reported devices was a fundamental limitation of the actuator chosen for those devices. A new actuator has been previously proposed by the authors that could potentially enable wavelength tuning over the full desired spectrum of 1.6-2.5 µm. This work reports measurements of devices fabricated using the new actuator design. The devices demonstrate that the measured tuning range exceeds the desired tuning range. The degradation mechanism in previously reported devices was identified as the oxidation of the silicon nitride in the MEMS actuator, which was deposited at 125°C to ensure compatibility with the HgCdTe substrate. In recent work, the filters have been fabricated on a silicon substrate with the aim of combining the MEMS substrate with the detectors using hybrid integration. Separating the MEMS fabrication from the detector fabrication relaxes the 125°C restriction on the deposition temperature of silicon nitride, allowing deposition at slightly higher temperatures, resulting in more stable material. The primary challenge that remains unresolved relates to the flatness of the mirrors that determine the finesse of the Fabry-Perot cavity. Any curvature or tilt of the movable mirror causes a reduction in transmission of the resonant wavelengths in the cavity and an increase in the linewidth of the transmitted light. The actuator that allows extended tuning in the recently fabricated devices is extremely susceptible to stress gradients, and the control over the stress gradient in the mirror material presents a processing challenge that has yet to be fully resolved. Stress compensation during the fabrication process is being investigated concurrently with post-fabrication stress gradient adjustment, with promising initial results.

4:30 PM C2-S4.2
Pulsed Current Electrochemical Deposition for Porous Silicon Capping: Method to Improve Hardness and Stability of Porous Silicon. (#392) Nihad K. Ali, MD Roslan Hashim, Azlan Abdul Aziz; School of Physics, Univesiti Sains Malaysia, Penang, Malaysia.

Abstract Single crystal silicon is being increasingly employed in a variety of new commercial products not because of its well established electronic properties, but rather because of its excellent mechanical properties. In addition, recent trends in the engineering literature indicate a growing interest in the use of porous silicon as a light emitter material with the ultimate goal of developing a broad range of inexpensive, easily interfaced with the rapidly proliferating microprocessor. The use of porous silicon has several drawbacks, namely its brittleness and the instability related to the aging process. In this paper we present a method to improve the stability of porous silicon structure by electrochemical deposition of silicon capping. Porous silicon is formed by pulse electrochemical etching of single crystalline silicon to provide an excellent control over the porosity and thickness of the individual layers. This was followed by pulsed current electrochemical deposition to provide uniform silicon capping layer on the porous structure. A linear relation between capping layer thickness and the deposition time was verified by cross section scanning electron microscopy. Hardness test was conducted to observe the stability of the capping layer on the porous structure, in which case the Vickers hardness has increased with increasing capping layer thickness. The spontaneous emission of the capped porous silicon will also be discussed.

4:45 PM C2-S4.3
Effect of Heat Treatment on Residual Stress in PECVD SiN_x Thin Films. (#901) Yimeng Yang, Yinong Liu, John Dell; The University of Western Australia, Australia.

Plasma enhanced chemical vapour deposition (PECVD) silicon nitride thin films are common structural materials for micro-electro-mechanical system (MEMS) devices. It has been found recently that the films are unstable in the ambient and may experience changes to their structures and properties. This study investigates the effect of low-temperature heating on the residual stresses of the films. It was found that PECVD SiNx thin films deposited at 473K and 573K developed tensile stressed after heating in air to temperatures above 373K. This is attributed to degassing of the films, which is expected to cause volume shrinkage, thus generating in-plane tensile stresses. Heating to above 873 K caused relaxation of the stresses, which is related to cracking of the films. Young's modulus and hardness are determined by nanoindentation method. Such damages limit the suitable application conditions for devices made of these films. On the other hand, these observations also suggest a possible means to stabilize the films by controlled heat treatment.